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MP7680
5 V CMOS 12-Bit Quad Double-Buffered Multiplying Digital-to-Analog Converter
June 2000-2
FEA TURES
* * * * * * * * *
Exar Pioneered Segmented DAC Approach Four Double-Buffered 12-bit DACs on a Single Chip Independent Reference Inputs Lowest Gain Error in a Multiple DAC Chip Guaranteed Monotonic TTL/5 V CMOS Compatible Inputs Industry Standard Digital Interface Four Quadrant Multiplication Latch-Up Free
BENEFITS
* Reduced Board Space; Lower System Cost. * Independent Control of DACs * Excellent DAC-to-DAC Matching and Tracking
APPLICA TIONS
* * * *
Function Generators Automatic Test Equipment Precision Process Controls Recording Studio Control Boards
GENERAL
DESCRIPTIONS
The MP7680 and the integrate four 12-bit four-quadrantmultiplying DACs with independent reference inputs and excellent matching characteristics. The MP7680 grades offer 1/2, 1 and 2 LSB of relative accuracy. The superior offers a low 2 LSB of gain error.
Each DAC has double-buffering (an 8 and 4-bit latch and a 12-bit latch) between the data bus (DB11 - DB0) and the DAC. The internal 4-bit mux allows the use of 8 or 16-bit buses. The flexible latch control logic allows to update one or more DACs simultaneously.
ORDERING
INFORMA
TION
Package Type
Temperature Range
Part No.
INL (LSB)
DNL (LSB)
Gain Error (LSB)
Plastic Dip Plastic Dip PQFP PQFP
-40 to +85C -40 to +85C -40 to +85C -40 to +85C
MP7680JN MP7680KN MP7680JE MP7680KE
+2 +1 +2 +1
+4 +2 +4 +2
+16 +16 +16 +16
Rev. 3.10
E1998
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7017
MP7680
DVDD AVDD RFBA IOUT1A IOUT2A VREFA RFBB IOUT1B IOUT2B VREFB RFBC IOUT1C IOUT2C VREFC RFBD IOUT1D IOUT2D VREFD
8-Bit Latch 4-Bit Latch 8-Bit Latch 4-Bit Latch
12-Bit Latch
DAC A
12-Bit Latch
DAC B
8-Bit Latch 4-Bit Latch DB11 - DB4 (MSB) 8 4 DB3 - DB0 (LSB) B1/B2 4 8 4 8-Bit Latch 4-Bit Latch 8 Input Latches Control
12-Bit Latch
DAC C
0 MUX 1
12-Bit Latch 1 DAC Latches Control
DAC D
A1 A0 CS WR2
XFER WR2
DGND AGND
Figure 1. Simplified
Block Diagram
Rev. 3.10 2
MP7680
PIN CONFIGURA TIONS
A1 XFER WR2 WR1 CS NC VREFA RFBA IOUT1A IOUT2A IOUT2B IOUT1B RFBB VREFB (MSB) DB11 DB10 DB9 DB8 DB7 DB6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
A0 B1/B2 DVDD AVDD DGND AGND VREFD RFBD IOUT1D IOUT2D IOUT2C IOUT1C RFBC VREFC DB0 (LSB) DB1 DB2 DB3 DB4 DB5
40 Pin PDIP , (0.600")
33
DGND AV DD DVDD B1/B2 AO NC A1 XFER WR2 WR1 CS
V REFD R FBD I OUT1D I OUT2D NC I OUT2C I OUT1C V FBC V REFC DBO
AGND
23 22
See the following page for pin descriptions
DB1 DB2 DB3 DB4 DB5 NC DB6 DB7 DB8 DB9 DB10
34
44 1 11
12
DB11 V REFB R FBB I OUT1B I OUT2B NC I OUT2A I OUT1A R FBA V REFA NC
44 Pin PQFP
Rev. 3.10 3
MP7680
PIN DESCRIPTION
40 Pin PDIP , CDIP
PIN NO. NAME DESCRIPTION
44 Pin PQFP
PIN NO. NAME DESCRIPTION
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
A1 XFER WR2 WR1 CS NC VREFA RFBA IOUT1A IOUT2A IOUT2B IOUT1B RFBB VREFB
DAC Address Bit 1 Transfer: Updates all DAC's Write 2: Gates the XFER Function Write 1: Gates the DAC Selection Chip Select No Connection Reference Input for DAC A Feedback Resistor for DAC A Current Output A Complement of Output A Complement of Output B Current Output B Feedback Resistor for DAC B Reference Input for DAC B
1 2 3 4 5 6 7 8 9 10 1116 17 1823 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
NC VREFA RFBA IOUT1A IOUT2A NC IOUT2B IOUT1B RFBB VREFB
No Connection Reference Input for DAC A Feedback Resistor for DAC A Current Output A Complement of Output A No Connection Complement of Output B Current Output B Feedback Resistor for DAC B Reference Input for DAC B
DB11 to Input Data Bits 11 (MSB) to 6 DB6 NC DB5DB0 VREFC RFBC IOUT1C IOUT2C NC IOUT2D IOUT1D RFBD VREFD AGND DGND AVDD DVDD B1/B2 A0 NC A1 XFER WR2 WR1 CS No Connection Input Data Bits 5 to 0 (LSB) Reference input for DAC C Feedback Resistor for DAC C Current Output C Complement of Output C No Connection Complement of Output D Current Output D Feedback Resistor for DAC D Reference input for DAC D Analog Ground Digital Ground Analog Power Supply Digital Power Supply Select Input Format (8/4 or 12 bits in) DAC Address Bit 0 No Connection DAC Address Bit 1 Transfer: Updates all DAC's Write 2: Gates the XFER Function Write 1: Gates the DAC Selection Chip Select
DB11 to Input Data Bits 11 (MSB) to 0 (LSB) DB0 VREFC RFBC IOUT1C IOUT2C IOUT2D IOUT1D RFBD VREFD AGND DGND AVDD DVDD B1/B2 A0 Reference input for DAC C Feedback Resistor for DAC C Current Output C Complement of Output C Complement of Output D Current Output D Feedback Resistor for DAC D Reference input for DAC D Analog Ground Digital Ground Analog Power Supply Digital Power Supply Select Input Format (8/4 or 12 bits in) DAC Address Bit 0
Rev. 3.10 4
MP7680
ELECTRICAL CHARACTERISTICS
= AGND = 0 V Unless
Tmin to Tmax Min Max
(V D D = + 5 V, V R E F = +10 V, I O U T 1 = I O U T 2 = DGND
25 C Parameter Symbol
1
Otherwise
Noted)
Min
Typ
Max
Units
Test Conditions/Comments
ST ATIC PERFORMANCE
Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) K J Differential Non-Linearity K J Gain Error K J Gain Temperature Coefficient2 Power Supply Rejection Ratio Output Leakage Current
DYNAMIC PERFORMANCE
2
N INL
12
12
Bits LSB Best Fit Straight Line Spec. (Max INL - Min INL) / 2
+1 +2 DNL +1 +4 GE +16 +16 TCGE PSRR IOUT +50 +50
+1 +2 LSB +2.0 +4.0 LSB +16 +16 +2 +70 +200 ppm/C ppm/% nA Using Internal RFB
DGain/DTemperature |DGain/DVDD| DVDD = + 5% IOUT1 VIN = 0 V IOUT2 VIN = VDD RL=100W, CEXT=13pF
Current Settling Time
REFERENCE INPUT
tS
1.0
ms
Full scale change to 1/2 LSB
Input Resistance Voltage Input Range2
DIGIT AL INPUTS
RIN VIN
3
5 +10
7 +25
3
7
kW V
Input High Voltage Input Low Voltage Input Current Input Capacitance2 Data Control
ANALOG OUTPUTS
2
ILKG CIN CIN 7.0 7.0
VIH VIL
2.4 0.8 +1
2.4 0.8 +4
V V mA pF pF
VIN = 0 V and VDD
Output Capacitance COUT1 COUT1 COUT2 COUT2 100 50 50 100 pF pF pF pF DAC all 1's DAC all 0's DAC all 1's DAC all 0's
Rev. 3.10 5
MP7680
ELECTRICAL CHARACTERISTICS (CONT'D)
25 C Tmin to Tmax
Parameter POWER SUPPL Y 4
Symbol
Min
Typ
Max
Min
Max
Units
Test Conditions/Comments
Functional Voltage Range Supply Current
TIMING CHARACTERISTICS
2, 3
VDD IDD
4.5
5.5 2 1
4.5
5.5 2 1
V mA mA
Digital inputs = VIL or VIH Digital inputs = 0 or 5 V
Write Pulse Width Chip Select Set-Up Time Address Set-Up Time Chip Select and Address Hold Time Latch Select Set-Up Time Latch Select Hold Time Data Valid Set-Up Time Data Valid Hold Time Transfer Pulse Width Write Cycle (per DAC)
Notes:
1 2 3 4
tWR tCS tAS tH tBS tBH tDS tDH
75 100 100 0 120 10 100 0 65 175
85 120 120 0 150 15 120 0 75 200
ns ns ns ns ns ns ns ns ns ns
tXFER tWC
Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. See timing diagram (Figure 2.). DV D D and AV D D are connected through the silicon substrate. Connect DC voltage differences will cause undesirable internal currents. Specifications are subject to change
together
at the package.
without
notice
ABSOLUTE
MAXIMUM
RA TINGS
(T A = +25
C
unless
otherwise
noted)
1, 2
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 V VDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to +7 V Digital Input Voltage to DGND . . . . GND -0.5 to VDD +0.5 V Any IOUT1, IOUT2 to AGND . . . . . . . GND -0.5 to VDD +0.5 V Any VREF to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V)
Any VRFB to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V Storage Temperature . . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . . +300C Package Power Dissipation Rating to 75C CDIP, PDIP, PQFP . . . . . . . . . . . . . . . . . . . . . . . . . 800mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 11mW/C
Notes:
1
2
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability . Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100 ms.
Rev. 3.10 6
MP7680
CS
tCS tAS
tH
NOTES:
tH tBH tDH
1. 2.
t XFER is the timing of the condition = Low . The timing of Figure the conditions 2. reproduces
XFER = WR2 graphically (see
A0, A1 B1/B2
VALID tBS tDS
that all control signals must meet writing cycles
in any of the many possible Theory of Operation).
DATA WR1
VALID tWR tWC
XFER tXFER WR2
Figure
2. W rite Cycle T iming
(Each DAC)
Rev. 3.10 7
MP7680
INPUT
LA TCHES
DAC LA TCHES
DB11-DB4 (MSB) DB11DB8 DB3-DB0 (LSB) 0 MUX 1
8 D 4 D Q B1 E Latch
LA11 - LA0 8 D E Q
DA11 - DA0 12 DAC
RFBA IOUT1A IOUT2A VREFA
B2 Q4 E Latch D 8 Q B1 E Latch D B2 Q4 E Latch D Q B1 E Latch D 8
8
DB11 - DB0 12 D E DC11 - DC0 12 D E DD11 - DD0 12 D E Q DAC Q DAC Q DAC
RFBB IOUT1B IOUT2B VREFB RFBC IOUT1C IOUT2C VREFC RFBD IOUT1D IOUT2D VREFD
4 8
4 8 B1/B2 Disable-B1 4 Enable A Latch Address Decoder Enable B Enable C Enable D
B2 Q4 E Latch D D Q B1 E Latch 8
B2 Q4 E Latch
A1 (MSB) A0 (LSB) CS WR1
Transfer
XFER WR2
Figure
3. Latches
Control
Logic
THEOR Y OF OPERA TION
Digital Interface W riting to Input Latches
Figure 3.
shows the internal control logic. The logic that controls the writing of the input latches and the one that controls the DAC latches are completely separated. It is easy to understand how the MP7680/80A works by understanding each basic operation.
By keeping B1/B2 = high, a 12-bit bus has direct access to the 12 bits of the input latches. The condition CS = WR1 = 0 loads the values contained in the data bus DB11-DB0 into the input latch addresses by A1, A0 (Figure 4. , Table 1. ).
Rev. 3.10 8
MP7680
SELECTED DAC
A1
A0
(Figure 5. ) During the second cycle the condition B1/B2 = low muxes DB11-DB8 to the B2 latches (Figure 3. ). Two important notes: 1) Timing diagrams show the inputs CS, A1, A0, DB11-DB0 to be stable during the entire writing cycle. In reality all the above signals can change (Figure 4. ) as long as they meet the timing conditions specified in the Electrical Characteristic Table. 2) Only 16-bit bus cycles are shown in the next few examples of interface timing. It is possible to generate an 8-bit interface timing by replacing a single 12-bit write cycle (Figure 4. ) with a double 8-bit write cycles (Figure 5. ) 8-bit applications should ground inputs DB3-DB0.
0 0 1 1
0 1 0 1
A B C D
Table 1. DAC Selection
An 8-bit bus must use two cycles. The second cycle is like the first one with the difference that B1/B2 = low
CS A1, A0 B1/B2 DATA WR1 High to B1 & B2
CS A1, A0
or
High
B1/B2 DATA WR1 to B1 to B2
Figure
4. 12 Bit W rite Cycle
Figure
5. 8-Bit Double
W rite Cycle
XFER WR2 DA11-0 IOUT tS
or
or
Figure
6. Transfer
Cycles
from Input Latches
to DAC Latches
Rev. 3.10 9
MP7680
Transferring Data to the DAC Latches
Once one or all of the input latches have been loaded, the condition XFER = WR2= low transfers the content of ALL the input latches in the DAC latches. The output of the DAC latches (DA11-DA0) changes and the DAC current (IOUT) will reach a new stable value within the settling time tS (Figure 6. ). Examples of DACs updating sequences: 1) Simultaneous updates of any number of DACs. The system uses from one (two) to four (eight) cycles to write from a 12 (8) bit bus into B1/B2 latches. One
transfer cycle updates the output of all DACs (Figure 7. ) 2) Individual DAC update. The condition WR2 = XFER = low makes the DAC latches transparent. A writing to the B1/B2 latches updates the DAC outputs (Figure 8. ). 3) Automatic transfer to DAC latches. An 8-bit bus can update any DAC with two cycles by connecting WR1 = WR2 and B1/B2= XFER. This is the correct individual DAC update for 8-bit busses (Figure 9. ). 4) Transfer by a second device. A processor may load the input latches while the final XFER pulse is left to another device.
CS A1, A0 CS A0, A1 DATA WR1 XFER=WR2 IOUT1A, B, C, D =0 Valid =1 Valid =2 Valid =3 Valid DATA WR1 WR2 = XFER IOUT1B IOUT1D =1 Valid =3 Valid
Figure
7. Simultaneous
Updates
of DACs
Figure
8. Individual
DAC Update
CS A1, A0 B1/B2 and XFER WR1 and WR2 IOUTB IOUTC =1 =2
Figure
9. Automatic
Transfer
to DAC Latches
Rev. 3.10 10
MP7680
+15 V 2 +10 V
REF01
RFBA VREFA +10 V 7 10k 14 10 V
8
6 10k
IOUT1A 9
DAC A
IOUT2A 10 RFBB 13 IOUT1B 12
+
VOUTA 0 V to -10 V
4 5k 5k 4
+
DAC B
VREFB VREFC 5V 27
IOUT2B 11 RFBC 28 IOUT1C 29
+
VOUTB 0 V to +10 V
+
DAC C
IOUT2C 30 RFBD 33 IOUT1D 32
+
VOUTC 0 V to +5 V
REF02
10k +5 V 2 +15 V 6
10k 34 +5 V VREFD
DAC D
IOUT2D 31
+
VOUTD 0 V to -5 V
Figure
10.
Digitally
Programmable
Quad Voltage
Output
+ 10 V, + 5 V
RFBA
DAC A
RA RFBB
Left Channel Input +
DAC B
+
Left Channel Output (+10 V MAX)
+
0.6 V +5 V
DAC A
+ 33k 10k
VOUTA
+ RFBC 10k RD RFBD +
10k
1.2 V
DAC B
+ 33k 10k + 33k 10k + 33k 10k
VOUTB
+ Right Channel Input
DAC C
MP5010 Right Channel Output (+10 V MAX) Matched Pairs: RFBA to RA RFBD to RD
DAC C
VOUTC
DAC D
+
DAC D
VOUTD
Figure
11. "Clickless"
Audio
Attenuator/Amplifier
Figure
12.
Quad DAC for Single
+5 V Supply
Rev. 3.10 11
MP7680 Notes
Rev. 3.10 12

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